SUPERCONDUCTING GATE MEMORY CIRCUIT

One embodiment includes a superconducting gate memory circuit. The circuit comprises a gate circuit configured to set a digital state as one of a first data state and a second data state in response to a presence of or absence of a write data single flux quantum, SFQ, pulse provided on a data write...

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Bibliographische Detailangaben
Hauptverfasser: Herr, Quentin P, Burnett, Randall M
Format: Patent
Sprache:eng ; fre ; ger
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Beschreibung
Zusammenfassung:One embodiment includes a superconducting gate memory circuit. The circuit comprises a gate circuit configured to set a digital state as one of a first data state and a second data state in response to a presence of or absence of a write data single flux quantum, SFQ, pulse provided on a data write input. The circuit further comprises a storage loop coupled to the gate circuit and configured to conduct a loop current having an amplitude that is set based on the digital state.