WOBBLE REDUCTION IN AN INTEGER MODE DIGITAL PHASE LOCKED LOOP

WOBBLE REDUCTION IN AN INTEGER MODE DIGITAL PHASE LOCKED LOOP

A circuit includes a time-to-digital converter (TDC) to produce an output signal that is a function of a time difference between a first input clock to the TDC and a second input clock to the TDC. A first delay line is also included to add a time delay to a third clock to produce the first input clo...

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Bibliographische Detailangaben
Hauptverfasser: JANARDHANAN, Jayawardan, LINDGREN, Eric, Paul, YAO, Henry
Format: Patent
Sprache:eng ; fre ; ger
Schlagworte:
AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATIONOF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
BASIC ELECTRONIC CIRCUITRY
ELECTRICITY
PULSE TECHNIQUE
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Zusammenfassung:A circuit includes a time-to-digital converter (TDC) to produce an output signal that is a function of a time difference between a first input clock to the TDC and a second input clock to the TDC. A first delay line is also included to add a time delay to a third clock to produce the first input clock. A pseudo random binary sequence generator generates a pseudo random binary bit sequence to be used to vary the amount of time delay added by the first delay line to the third clock.