METHOD OF CHECKING EQUIVALENCE BETWEEN A FIRST DESIGN COMPRISING A SHIFT REGISTER LOGIC SRL CHAIN AND A SECOND DESIGN COMPRISING A MEMORY BLOCK

METHOD OF CHECKING EQUIVALENCE BETWEEN A FIRST DESIGN COMPRISING A SHIFT REGISTER LOGIC SRL CHAIN AND A SECOND DESIGN COMPRISING A MEMORY BLOCK

The present invention proposes a method of checking equivalence between a first design comprising a shift register logic SRL chain and a second design comprising a memory block. The method comprises identifying an inductive invariant to replace the SRL chain or the memory block, and replacing the SR...

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser: Chandrasekharan, Arun, Welp, Tobias, Warkentin, Peter
Format: Patent
Sprache:eng ; fre ; ger
Schlagworte:
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Beschreibung
Zusammenfassung:The present invention proposes a method of checking equivalence between a first design comprising a shift register logic SRL chain and a second design comprising a memory block. The method comprises identifying an inductive invariant to replace the SRL chain or the memory block, and replacing the SRL chain and the memory block by a set of constraints, wherein the set of constraints state that the SRL chain and the memory block are equivalent for the checking of equivalence between the first design and the second design