SYSTEMS AND METHODS FOR LOW LATENCY HARDWARE MEMORY MANAGEMENT

In various embodiment, the present invention teaches a sequencer that identifies an address point of a first data block within a memory and a length of data that comprises that data block and is related to an input of a matrix processor. The sequencer then calculates, based on the block length, the...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	BANNON, Peter Joseph, HURD, Kevin Altair, TALPES, Emil
Format:	Patent
Sprache:	eng ; fre ; ger
Schlagworte:	CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS
Online-Zugang:	Volltext bestellen
Tags:	Tag hinzufügen Keine Tags, Fügen Sie den ersten Tag hinzu!