SYSTEMS AND METHODS FOR LOW LATENCY HARDWARE MEMORY MANAGEMENT

In various embodiment, the present invention teaches a sequencer that identifies an address point of a first data block within a memory and a length of data that comprises that data block and is related to an input of a matrix processor. The sequencer then calculates, based on the block length, the...

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser: BANNON, Peter Joseph, HURD, Kevin Altair, TALPES, Emil
Format: Patent
Sprache:eng ; fre ; ger
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Beschreibung
Zusammenfassung:In various embodiment, the present invention teaches a sequencer that identifies an address point of a first data block within a memory and a length of data that comprises that data block and is related to an input of a matrix processor. The sequencer then calculates, based on the block length, the input length, and a memory map, a block count representative of a number of data blocks that are to be retrieved from the memory. Using the address pointer, the sequencer may retrieve a number of data blocks from the memory in a number of cycles that depends on whether the data blocks are contiguous. In embodiments, based on the length of data, a formatter then maps the data blocks to the input of the matrix processor.