CHIP AND PACKAGING METHOD

Embodiments of this application disclose a chip and a packaging method thereof. In the chip, first solder pads in a first solder pad array on a first substrate are attached to corresponding second pins in second pin arrays on different dies, to implement short-distance and high-density interconnection of the different dies. A molding body is used to wrap a first pin, a second pin, a first solder pad, and the first substrate, so that a fan-out unit and the first substrate are molded into an integral structure. In the integral structure, bottoms of first pins that are in a first pin array on a die and that are electrically connected to a periphery of the chip are not wrapped by the molding body. In this way, the first pins may be directly electrically connected to the periphery of the chip. An overall size of the chip provided in the embodiments of this application mainly depends on a size of a plurality of dies integrated together. The overall size of the chip provided in the embodiments of this application is smaller than that of a chip in the prior art, and a requirement on chip miniaturization can be met.