MULTI-CHIP-PACKAGE

A package comprises: a package body (20) with a package top side (201), a package footprint side (202) and package sidewalls (203), the package sidewalls (203) extending from the package footprint side (202) to the package top side (201); a plurality of power semiconductor chips (100) electrically connected in parallel to each other, each power semiconductor chip (100) having a first load terminal (101) and a second load terminal (102) and being configured to block a blocking voltage applied between said load terminals (101, 102) and to conduct a chip load current between said load terminals (101, 102); a lead frame structure configured to electrically and mechanically couple the package (200) to a carrier (300) with the package footprint side (202) facing to the carrier (300), the lead frame structure (31) comprising a first load terminal bar (211) and at least one first outside terminal (2111), the at least one first outside terminal (2111) extending out of the package body (20) for interfacing with the carrier (300) and being electrically connected with each of the first load terminals (101) of the plurality of power semiconductor chips (100) by means of the first load terminal bar (211). The plurality of power semiconductor chips (100) are arranged horizontally adjacent to each other along a first lateral direction (X) in the package body (20). The first load terminal bar (211) extends along the first lateral direction (X) so as to subsequently establish electrical contact with the first load terminals (101) of the power semiconductor chips (100).