MEMORY ARRAYS

A memory array comprising a plurality of memory cells. Each of the memory cells comprises a transistor and a capacitor structure and being disposed within one memory cell tier comprised by a plurality memory cell tiers. The plurality of memory cell tiers are stacked in a vertical direction. A capacitor electrode structure extends in the vertical direction through the plurality of memory cell tiers. A conductive-line structure extends in the vertical direction through the plurality of memory cells. Individual of the memory cells comprised by the plurality of memory cells comprise a region extending between the capacitor electrode structure and the conductive-line structure along a horizontal direction. The region comprises, in the following order, the capacitor structure electrically coupled to the capacitor electrode structure, a first source/drain region, a transistor channel region, and a second source/drain region electrically coupled to the conductive-line structure.