METHOD AND APPARATUS FOR GENERATING CLOCK

A clock generation apparatus includes a pulse generator (420) configured to generate a pulse signal (PUL) and a selection signal (SEL) using a reference clock signal (CK_R), a delay line circuit (440; 440a; 440b), a switch (300) and a controller (500). The delay line circuit (440; 440a; 440b) selects, as an input signal to a delay path, the pulse signal (PUL) or a fed back portion of a delay clock signal (CK_DL) at an output of the delay path, where the selection is based on the selection signal (SEL); and thereby generates the delay clock signal (CK_DL). The switch (300) switches a first voltage (V1) or a second voltage (V2) to the delay line circuit (440; 440a; 440b) for its operation, where the first voltage (V1) further provides power to the pulse generator (420). The second voltage (V2) is generated based on a phase difference between the reference clock signal (CK_R) and the delay clock signal (CK_DL). The controller (500) generates a switch control signal (C_SW) based on a frequency of the delay clock signal (CK_DL).