SYSTEMS, METHODS, AND APPARATUSES FOR HETEROGENEOUS COMPUTING

SYSTEMS, METHODS, AND APPARATUSES FOR HETEROGENEOUS COMPUTING

The present disclosure provides a processor including a processor core. The processor core includes: a decoder to decode at least one instruction native to the processor core; one or more execution units to execute at least one decoded instruction, the at least one decoded instruction corresponding...

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser: CHARNEY, Mark J, NUZMAN, Joseph, VALENTINE, Robert, VAN DOREN, Stephen R, MOSUR, Lokpraveen B, MISHRA, Asit K, SANKARAN, Rajesh M, O'HANLON, Michael A, CORBAL, Jesus, MCDONNELL, Niall D, RANGANATHAN, Narayan, MANLEY, Dwight P, MARR, Deborah T, NURVITADHI, Eriko, VENKATESH, Ganesh, GROCHOWSKI, Edward T, GLOSSOP, Kent D, SHEFFIELD, David B, NEIGER, Gilbert, CAPRIOLI, Paul, GRECO, Richard J, PEARCE, Jonathan D, CARTER, Nicholas P, FLETCHER, Thomas D, YAMADA, Koichi, BRADFORD, Dennis R, COOK, Jeffrey J, DRYSDALE, Tracy Garrett
Format: Patent
Sprache:eng ; fre ; ger
Schlagworte:
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Beschreibung
Zusammenfassung:The present disclosure provides a processor including a processor core. The processor core includes: a decoder to decode at least one instruction native to the processor core; one or more execution units to execute at least one decoded instruction, the at least one decoded instruction corresponding to an acceleration begin instruction, the acceleration begin instruction to indicate a start of a region of code to be offloaded to an accelerator.