BIMODAL PHY FOR LOW LATENCY IN HIGH SPEED INTERCONNECTS

Systems, methods, and apparatuses involve a PHY (1000) coupled to a MAC (1100). For example, an apparatus is provided, comprising: a PHY block (1000) comprising a plurality of PHY PIPE registers, a MAC block (1100) comprising a plurality of MAC PIPE registers, and a PHY/MAC interface to interface the PHY block (1000) and the MAC block (1100). The PHY/MAC interface comprises: a first set of wires to transfer a plurality of register commands between the PHY block and the MAC block, at least some of the plurality of register commands comprising command, address and data to be transferred via the first set of wires over a plurality of clock cycles; and a second set of wires dedicated to transfer datapath signals between the PHY block and the MAC block. In a first mode, the PHY block (1000) is to send data and a PCLK (1102) to the MAC block (1100). In a second mode, the PHY block (1000) is to send data and a recovered clock (1016) to the MAC block (1100).