CACHE CONTROL IN PRESENCE OF SPECULATIVE READ OPERATIONS

Coherency control circuitry 10 supports processing of a safe-speculative-read transaction received from a requesting master device 4. The safe-speculative-read transaction is of a type requesting that target data is returned to a requesting cache 11 of the requesting master device 4 while prohibiting any change in coherency state associated with the target data in other caches 12 in response to the safe-speculative-read transaction. In response, at least when the target data is cached in a second cache associated with a second master device, at least one of the coherency control circuitry 10 and the second cache 12 is configured to return a safe-speculative-read response while maintaining the target data in the same coherency state within the second cache. This helps to mitigate against speculative side-channel attacks.