POWER SEMICONDUCTOR MODULE

Power semiconductor module, including a base plate with at least one substrate located on the base plate, wherein an electronic circuit is provided on the at least one substrate, wherein located on the at least one substrate are electrical connectors comprising a DC+ power terminal, a DC− power term...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: HARTMANN, Samuel, TRUESSEL, Dominik
Format: Patent
Sprache:eng ; fre ; ger
Schlagworte:
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
Beschreibung
Zusammenfassung:Power semiconductor module, including a base plate with at least one substrate located on the base plate, wherein an electronic circuit is provided on the at least one substrate, wherein located on the at least one substrate are electrical connectors comprising a DC+ power terminal, a DC− power terminal and an AC power terminal and further a control connector, wherein the power semiconductor module is designed as a half-bridge module including a first amount of switching power semiconductor devices and a second amount of switching power semiconductor devices, wherein the base plate includes a contact area, a first device area and a second device area, wherein the contact area is positioned in a center of the base plate such, that the first device area is positioned at a first side of the contact area and that the second device area is positioned at a second side of the contact area, the second side being arranged opposite to the first side, wherein the DC+ power terminal, the DC− power terminal, the AC power terminal and the control connector are positioned in the contact area, wherein the first amount of switching power semiconductor devices is positioned in the first device area and wherein the second amount of switching power semiconductor devices is positioned in the second device area, wherein all the power semiconductor devices in the first device area are located in two parallel lines being aligned parallel to the width of the base plate and wherein all the power semiconductor devices in the second device area are located in two parallel lines being aligned parallel to the width of the base plate.