MEMORY ACCESS TECHNIQUE

A memory access technology is provided, applied to a computer system including a first-level memory, a second-level memory, and a memory controller. The first-level memory is configured to cache data in the second-level memory. In the memory access technology, for a plurality of access requests for accessing different memory blocks having a mapping relationship with a first cache line in the first-level memory, the memory controller may compare tags of the plurality of access requests with a tag of the first cache line in a centralized manner, to determine whether the plurality of access requests hit the first-level memory. When processing the plurality of access requests, the memory controller needs to read the tag of the first cache line from the first-level memory only once, thereby reducing a quantity of times of reading the tag of the first cache line from the first-level memory, shortening memory access latency, and improving memory access efficiency.