A LED DRIVER CIRCUIT, CORRESPONDING DEVICE AND METHOD

A LED driver circuit comprises a set of LED driver devices (#1, #2, ...) comprising a finite state machine or FSM (22) generating LED drive PWM-modulated signal patterns (CHx) and an oscillator (18) to generate a clock signal (osc_out) for the FSM (22). The LED driver devices are coupled (SDA, SCL)...

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Bibliographische Detailangaben
Hauptverfasser: ADAMO, Santi Carlo, CALA', Ignazio
Format: Patent
Sprache:eng ; fre ; ger
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Zusammenfassung:A LED driver circuit comprises a set of LED driver devices (#1, #2, ...) comprising a finite state machine or FSM (22) generating LED drive PWM-modulated signal patterns (CHx) and an oscillator (18) to generate a clock signal (osc_out) for the FSM (22). The LED driver devices are coupled (SDA, SCL) via a bus (I2C bus) with bus pins (I2C) coupled to the bus (SDA, SCL), while also including a set of slave address pins (A0, A1). The LED driver devices (#1, #2, ..) comprise a first signal path (14, 20) activatable (en_A1, chain_in_en) between the first (A1) slave address pin and the FSM (22) as well as a second signal path (12, 16) activatable (en_A0, chain_out_en) between the FSM (22) and the second (A0) slave address pin. A controller (MC) has general-purpose input/output nodes (A, B, C) coupled to the slave address pins (A0, A1) in the LED driver devices (#1, #2, ...) with the controller (MC) configured to provide via the slave address pins (A0, A1) of the LED driver devices in the set of LED driver devices (#1, #2, ...) at least one inter-device clock signal propagation path from the second slave address pin (A0) in one LED driver device (#1, #2, ...) in the set of LED driver devices (#1, #2, ...) to the first slave address pin (A1) in another (#2, #3 ...) LED driver device in the set of LED driver devices (#1, #2, ...). A clock signal (osc_out; EXT CLK) coupled to the FSM (22) in one (#1, #2 ...) LED driver device is coupled to the FSM (22) in another (#2;#3 ...) LED driver device via the activated second signal path (12, 16) and first signal path (14, 20) and the at least one inter-device clock signal propagation path.