CLOCK DISTRIBUTION CIRCUIT FOR DUTY CYCLE CORRECTION

Clock distribution circuitry (10) configured for duty cycle control, the circuitry comprising: a plurality of buffers (20, 40) connected in series along a clock path having an input node (CLKIN) and an output node (CLKOUT), each of the buffers having an input terminal and an output terminal, the input terminal being connected to the clock path via a corresponding AC coupling capacitor, and the clock path configured to receive an input clock signal at the input node and output an output clock signal at the output node, the output clock signal having an output duty cycle; and control circuitry (200) connected to apply a DC bias signal to the input terminal of each of the plurality of buffers, wherein the control circuitry is configured to: obtain a measurement signal indicative of the output duty cycle; and control the DC bias signals, based on a difference between the measurement signal and a reference signal, so as to control the output duty cycle.