LOAD-BALANCED TESSELLATION DISTRIBUTION FOR PARALLEL ARCHITECTURES

LOAD-BALANCED TESSELLATION DISTRIBUTION FOR PARALLEL ARCHITECTURES

Briefly, in accordance with one or more embodiments, an architecture to load balance tessellation distribution apparatus comprises a memory to store one or more patches representing an object in an image, and a processor, coupled to the memory, to perform one or more tessellation operations on the o...

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser: AKENINE-MOLLER, Tomas G, MUNKBERG, Carl J, HASSELGREN, Jon N
Format: Patent
Sprache:eng ; fre ; ger
Schlagworte:
CALCULATING
COMPUTING
COUNTING
IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
PHYSICS
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Beschreibung
Zusammenfassung:Briefly, in accordance with one or more embodiments, an architecture to load balance tessellation distribution apparatus comprises a memory to store one or more patches representing an object in an image, and a processor, coupled to the memory, to perform one or more tessellation operations on the one or more patches. The one or more tessellation operations including splitting one or more of the patches into one or more subpatches, and load balancing the one or more patches and the one or more subpatches among two or more geometry and setup fixed-function pipelines (GSPs).