METHODS AND SYSTEMS FOR PERFORMING A CALCULATION ACROSS A MEMORY ARRAY

Devices for computing the sum of multiple Vector-Vector Dot-Products (VVDP) or multiple partial sums of VVDP can include a resistive memory array and a reduction circuit. The reduction circuit can be configured to determine a sum of a selected one or more of a plurality of bit lines of the resistive...

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Bibliographische Detailangaben
Hauptverfasser:	SRINIVASAN, Srikanth T, TOMISHIMA, Shigeki
Format:	Patent
Sprache:	eng ; fre ; ger
Schlagworte:	BASIC ELECTRONIC CIRCUITRY CALCULATING CODE CONVERSION IN GENERAL CODING COMPUTER SYSTEMS BASED ON SPECIFIC COMPUTATIONAL MODELS COMPUTING COUNTING DECODING ELECTRICITY INFORMATION STORAGE PHYSICS STATIC STORES
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Beschreibung
Zusammenfassung:	Devices for computing the sum of multiple Vector-Vector Dot-Products (VVDP) or multiple partial sums of VVDP can include a resistive memory array and a reduction circuit. The reduction circuit can be configured to determine a sum of a selected one or more of a plurality of bit lines of the resistive memory array. A VVDP reduction can be determined from the sum of the selected one or more of the plurality of bit lines.