POWER SEMICONDUCTOR MODULE ARRANGEMENT

A power semiconductor module arrangement comprises a housing comprising sidewalls and a substrate arranged in the housing, the substrate comprising a dielectric insulation layer, a first metallization layer arranged on a first side of the dielectric insulation layer, and a second metallization layer arranged on a second side of the dielectric insulation layer, wherein the dielectric insulation layer is disposed between the first and the second metallization layer. The arrangement further comprises at least one semiconductor body mounted on a first surface of the first metallization layer which faces away from the dielectric insulation layer, a contact element that is mechanically and electrically connected to the substrate, wherein the contact element extends from the substrate through the interior of the housing to the outside of the housing in a direction perpendicular to the first surface, and at least two guiding elements coupled to the housing. If a printed circuit board comprising first and second through holes is mounted to the power semiconductor module arrangement, the guiding elements are configured to be inserted into the second through holes, thereby serving as an insertion aid that accurately aligns the printed circuit board and the contact element, and the guiding elements are further configured to securely hold the printed circuit board in a final mounting position on the power semiconductor module arrangement and prevent any vertical and horizontal movements of the printed circuit board when the printed circuit board is arranged in its final mounting position.