TECHNOLOGIES FOR PERFORMING PARTIALLY SYNCHRONIZED WRITES

The present disclosure provides an apparatus comprising a plurality of processing cores integrated onto multiple integrated circuit dies in a package, the plurality of processing cores to execute instructions and process data, memory logic to couple to a memory device, a coherent interconnect fabric to connect the plurality of processing cores and the memory logic and a physical, PHY, layer interface. The physical, PHY, layer interface comprising a plurality of connectors coupled to a plurality of data lanes, the plurality of connectors including a first subset of the connectors to communicate in accordance with a first interconnect protocol, a second subset of the connectors to communicate in accordance with a second interconnect protocol, and a third subset of the connectors to communicate in accordance with a third interconnect protocol. The apparatus comprising a first logical sub-block to encode data in accordance with the first interconnect protocol, a second logical sub-block to encode data in accordance with the second interconnect protocol and a third logical sub-block to encode data in accordance with the third interconnect protocol and a multiplexer. The multiplexer is to connect the first subset of connectors to the first logical sub-block, to connect the second subset of the connectors to the second logical sub-block, and to connect the third subset of the connectors to the third logical sub-block. The apparatus comprising a first transaction layer to communicate data between the coherent interconnect fabric and the first logical sub-block in accordance with the first interconnect protocol; a second transaction layer to communicate data between the coherent interconnect fabric and the second logical sub-block in accordance with the second interconnect protocol; and a third transaction layer to communicate data between the coherent interconnect fabric and the third logical sub-block in accordance with the third interconnect protocol.