SEMICONDUCTOR ARRANGEMENT WITH RELIABLY SWITCHING CONTROLLABLE SEMICONDUCTOR ELEMENTS

A semiconductor arrangement includes a circuit board comprising a metallization layer with a first conductor track and a second conductor track, and a multiplicity of individual semiconductor chips (1) each comprising a controllable semiconductor element (T), a first load electrode (11), a second load electrode (12) and a control electrode (13), the first load electrodes (11) of the individual semiconductor chips (1) electrically connected to one another, the second load electrodes (12) of the individual semiconductor chips (1) electrically connected to one another, and the control electrodes (13) of the individual semiconductor chips (1) electrically connected to one another. The first conductor track (M1) includes a base section (30) and a first, second and third section (31, 32, 33), the third section (33) arranged between the first and second sections (31, 32), and the second conductor track (M2) includes a first and a second section (41, 42). The first section (41) of the second conductor track (M2) is arranged between the first and the third section (31, 33) of the first conductor track (Ml), the second section (42) of the second conductor track (M2) is arranged between the second and the third section (32, 33) of the first conductor track (Ml), and the third section (33) of the first conductor track (M1) is arranged between the first and the second section (41, 42) of the second conductor track (M2). A first subset and a second subset of the multiplicity of semiconductor chips (1) are arranged on the first section (41) of the second conductor track (M2), and a third subset and a fourth subset of the multiplicity of semiconductor chips (1) are arranged on the second section (42) of the second conductor track (M2). The first load electrode (11) of each of the semiconductor chips (1) of the first and the second subset is, via at least one first electrical connection (51, 52), electrically connected to the first section (31) of the first conductor track (M1) and, via at least one second electrical connection (51, 52), to the third section (33) of the first conductor track (M1). Further, the first load electrode (11) of each of the semiconductor chips (1) of the third and the fourth subset is, via at least one third electrical connection (51, 52), electrically connected to the third section (33) of the first metallization (M1) and, via at least one fourth electrical connection (51, 52), to the second section (32) of the first conductor track (M1).