HARDWARE UNIT FOR PERFORMING MATRIX MULTIPLICATION WITH CLOCK GATING

Hardware units and methods to perform matrix multiplication between a first matrix of first data elements and a second matrix of second data elements. The hardware unit includes: a multiplier stage comprising a plurality of multipliers, each multiplier configured to multiply a first data element and a second data element to produce a multiplication data element; one or more adder stages following the multiplier stage that form an adder tree to produce a sum of the multiplication data elements, each adder stage comprising one or more adders configured to add at least two data elements output by a previous stage to produce an addition data element; and control logic. At least one of the adders is preceded by a storage element corresponding to each bit of the data elements input to the at least one adder. The control logic is configured to clock gate all of the storage elements corresponding to a data element input to an adder of the at least one adder in response to determining that the data element has a zero value, independent of whether the other data element input to that adder has a zero value.To be accompanied, when published, by FIG. 6 of the accompanying drawings.