TUPLE ENCODING AWARE DIRECT MEMORY ACCESS ENGINE FOR SCRATCHPAD ENABLED MULTICORE PROCESSORS

A data processing core that is coupled with a first on-chip memory pushes a particular memory address of a descriptor into a first register within a first register space that is accessible by a first set of electronic circuits that is coupled to said on-chip memory. The descriptor indicates a width of a column of tabular data, a number of rows of said tabular data, and a data manipulation operation to perform on said tabular data. In response to said particular memory address of said descriptor being pushed into said first register by said data processing core (601a), the first set of electronic circuits accesses, using the particular memory address in the first register, the descriptor in the first on-chip memory (601b), and the first set of electronic circuits determines, based on the descriptor, control information indicating one or more data manipulation operations to perform (602).