MULTIPLE MASTER PROCESS CONTROLLERS USING A SHARED SERIAL PERIPHERAL BUS

A fault-tolerant process control system 200 includes a first and second master process controller 110, 110' each including a first and second serial communication engine 117, 117'. A first bus switch 211 couples the first serial communication engine to a shared SPI bus 235 and a second bus switch 212 couples the second communication engine to shared SPI bus. The shared SPI bus transmits SPI signals received from the first serial communication engine when the first bus switch 211 is enabled to a first target device 120, and transmits SPI signals received from the second serial communication engine when the second bus switch 212 is enabled to a second target device 120'. An arbiter block 225 receives a select control signal from the master process controllers and is coupled to both the first and second bus switch for single bus switch selection so that only one master process controller is granted access to the shared SPI bus.