AN IP-GPIO SYSTEM, CORRESPONDING APPARATUS AND METHOD

A system, such as a System-on-Chip (SoC) includes a plurality of analog Intellectual Property circuits (IPa, IPb) and a General Purpose Input/Output circuit (GPIO) shared by the plurality of Intellectual Property circuits via respective analog links (AINa, AINb). Analog switches (A, B) coupled with the analog links (AINa, AINb) control signal propagation over the respective analog links. The analog switches (A, B) are activatable via switch enable signals (AIN_ENa, AIN ENb) over respective switch enable paths having a first end coupled to one of the Intellectual Property circuits (IPa, IPb) and a second end coupled to the shared General Purpose Input/Output circuit (GPIO). One or more of the switch enable paths include a secure analog link circuit (SAL1, SAL2) sensitive to the secure/non-secure status (IP_sec, IO_sec) of the Intellectual Property circuit (IPa, IPb) and the General Purpose Input/Output circuit (GPIO) coupled to the ends of the switch enable paths. The secure analog link circuit(s) are configured to admit propagation of a switch enable signal as a result of the Intellectual Property circuit (IPa, IPb) and the General Purpose Input/Output circuit (GPIO) coupled to the ends of the switch enable path having both secure status or both non-secure status.