LOW-POWER DATA BUS RECEIVER

The present invention relates to a circuit (24) for receiving and processing a bit stream (34) obtained from an electronic communication bus-system (20). The circuit comprises a bit stream processing unit (5) for synchronization and bit sampling of the bit stream (34) to provide a sampled output signal (52). The circuit comprises a frame decoding unit (6) for decoding a data frame encoded in the sampled output signal (52). The circuit comprises a clock signal generator (19) for generating a first clock signal (32) for the bit stream processing unit (5). The circuit comprises a clock signal downsampler (51) for generating a second clock signal (60) having a lower frequency than the first clock signal, in which the second clock signal (60) is based on a cooccurrence of a clock pulse in the first clock signal (32) and the emission of a bit in the sampled output signal. The second clock signal is provided to the frame decoding unit (6). The bit stream processing unit (5) is adapted for synchronizing the first clock signal (32) to an external protocol timing of the incoming bit stream.