METHOD AND APPARATUS FOR USER-LEVEL THREAD SYNCHRONIZATION WITH A MONITOR AND MWAIT ARCHITECTURE

Instructions and logic provide user-level thread synchronization with MONITOR and MWAIT instructions. For example, a processor comprises: a data cache; an instruction cache; instruction fetch circuitry to fetch the MONITOR instruction and the MWAIT instruction from the instruction cache; instruction decode circuitry to decode the fetched MONITOR instruction and MWAIT instruction; a model specific register (MSR) to be configured in a user-monitor-wait-enabled execution state to enable the MONITOR instruction and the MWAIT instruction to be executed at a privilege level; and execution circuitry to execute the MONITOR instruction and the MWAIT instruction. When the MSR is not configured in the user monitor-wait-enabled execution state, execution of the MONITOR instruction and the MWAIT instruction is restricted to the privilege level zero. The MONITOR instruction is to specify a linear address range to be monitored, the linear address range to have a write-back memory type for caching in the data cache. The MWAIT instruction is to specify an implementation-dependent-optimized state for power management and to indicate to the processor to enter the implementation-dependent-optimized state for power management. The execution circuitry is configured to detect a store operation to the linear address range, and if the implementation-dependent-optimized state for power management is entered in response to execution of the monitor-wait instruction, the implementation-dependent-optimized state for power management is maintained until the store operation to the linear address range is detected.