METHOD FOR LOW-TEMPERATURE POLYCRYSTALLINE SILICON THIN FILM TRANSISTOR

A LTPS TFT, a method for fabricating the same, an array substrate, a display panel, and a display device are disclosed. The LTPS TFT comprises an active layer, a source, a drain, a gate, and a gate insulating layer which are arranged on a substrate, the gate insulating layer is arranged between the...

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Bibliographische Detailangaben
Hauptverfasser: CHAN, Yucheng, ZHANG, Shuai
Format: Patent
Sprache:eng ; fre ; ger
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Zusammenfassung:A LTPS TFT, a method for fabricating the same, an array substrate, a display panel, and a display device are disclosed. The LTPS TFT comprises an active layer, a source, a drain, a gate, and a gate insulating layer which are arranged on a substrate, the gate insulating layer is arranged between the active layer and the gate, and a graphene oxide layer which is arranged between the active layer and the gate insulating layer. Since the graphene oxide layer is arranged between the active layer and the gate insulating layer, the interface between the P-Si active layer and the gate insulating layer has a reduced roughness and interfacial defect density, and a pre-cleaning process is not necessary for the gate insulating layer.