TRANSMISSION ARRANGEMENT FOR FULL-DUPLEX COMMUNICATION

The present invention relates to a transmission arrangement (100) for coupling a pair of transmit output terminals (101, 102) to a pair of medium terminals (103, 104) coupled a transmission medium (40), and the pair of medium terminals to a pair of receive input terminals (105, 106), the pairs of tr...

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Bibliographische Detailangaben
Hauptverfasser: TYTGAT, Maarten, STRACKX, Maarten, GURNE, Thibaut
Format: Patent
Sprache:eng ; fre ; ger
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Zusammenfassung:The present invention relates to a transmission arrangement (100) for coupling a pair of transmit output terminals (101, 102) to a pair of medium terminals (103, 104) coupled a transmission medium (40), and the pair of medium terminals to a pair of receive input terminals (105, 106), the pairs of transmit output terminals, receive input terminals and medium terminals carrying opposite-polarity signals (±V TX ; ±V RX ; ±V LINE ) . In accordance with an embodiment of the invention, the transmission arrangement comprises a first adder (110) and a second adder (120) with respective first and second adder input terminals (111, 121; 112, 122) and respective adder output terminals (114; 124). The pair of transmit output terminals is coupled to the pair of first adder input terminals, and is further coupled through respective first impedances (Z 1 ) to the pair of second adder input terminals and to the pair of medium terminals, with the first and second adder input terminals being respectively coupled to opposite-polarity transmit output terminals. The pair of receive input terminals is coupled to the pair of adder output terminals. The first impedances individually comprise a first resistor (R 1 ) coupled in parallel with a first capacitor (C 1 ). The first and second adders individually comprise second and third capacitors (C 2 , C 3 ) between the respective first and second adder input terminals and a common terminal (115; 125), and a feedback network between the adder output terminal and the common terminal. The first capacitors have a reactance value that matches the difference between the reactance values of the second and third capacitors.