SEAMLESS ADDITION OF HIGH BANDWIDTH LANES

SEAMLESS ADDITION OF HIGH BANDWIDTH LANES

Seamless addition of high bandwidth lanes, including the steps of: sending, by a master, an idle sequence using 7b/10b code words over new high bandwidth lanes in parallel to sending and receiving 8b/10b data with a fixed delay over master-to-slave (m2s) and slave-to-master (s2m) active high bandwid...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: LIDA, Eyran, SALAMON, Aviv
Format: Patent
Sprache:eng ; fre ; ger
Schlagworte:
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Beschreibung
Zusammenfassung:Seamless addition of high bandwidth lanes, including the steps of: sending, by a master, an idle sequence using 7b/10b code words over new high bandwidth lanes in parallel to sending and receiving 8b/10b data with a fixed delay over master-to-slave (m2s) and slave-to-master (s2m) active high bandwidth lanes; sending in parallel a synchronization sequence and a known non-idle sequence during an inter packet gap; utilizing, by the slave, the known non-idle sequence for deskewing the new high bandwidth lanes; and sending, by the master, a transition sequence over both the m2s active high bandwidth lane and the new high bandwidth lanes, and immediately thereafter the master is ready to transmit high bandwidth data using 8b/10b code words over both the m2s active high bandwidth lane and the new high bandwidth lanes.