MEMORY CELL AND NON-VOLATILE SEMICONDUCTOR STORAGE DEVICE

A memory cell and a non-volatile semiconductor memory device are disclosed. Nitride sidewall layers (32a and 32b) are respectively disposed in a first sidewall spacer (28a) and a second sidewall spacer (28b), to separate a memory gate electrode (MG) and a first select gate electrode (DG) from each other and the memory gate electrode (MG) and a second select gate electrode (SG) from each other. Hence, a breakdown voltage is improved around the memory gate electrode (MG) as compared with a conventional case in which the first sidewall spacer (28a) and the second sidewall spacer (28b) are simply made of insulating oxide films. The nitride sidewall layers (32a and 32b) are disposed farther from a memory well (MW) than a charge storage layer (EC). Hence, charge is unlikely to be injected into the nitride sidewall layers (32a and 32b) at charge injection from the memory well (MW) into the charge storage layer (EC), thereby preventing an operation failure due to charge storage in a region other than the charge storage layer (EC).