SAMPLE-AND-HOLD CIRCUIT

SAMPLE-AND-HOLD CIRCUIT

A sample-and-hold circuit, which includes a hold capacitor at its output terminal and at least one intermediate capacitor, intermittently receives an input voltage, and a first value of a switch enable signal causes the sample-and-hold circuit to sample the input voltage and to charge the at least o...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: Saez, Richard Titov Lara, Olarte Gonzalez, Javier Mauricio, Vilas Boas, Andre Luis
Format: Patent
Sprache:eng ; fre ; ger
Schlagworte:
CONTROLLING
INFORMATION STORAGE
PHYSICS
REGULATING
STATIC STORES
SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
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Beschreibung
Zusammenfassung:A sample-and-hold circuit, which includes a hold capacitor at its output terminal and at least one intermediate capacitor, intermittently receives an input voltage, and a first value of a switch enable signal causes the sample-and-hold circuit to sample the input voltage and to charge the at least one intermediate capacitor and the hold capacitor to the input voltage, and when it is not receiving the input voltage, a second value of the switch enable signal causes the sample-and-hold circuit to hold, at its output terminal, the input voltage until the hold capacitor discharges, which starts to discharge only after the at least one intermediate capacitor has substantially discharged.