RESERVATION STATION HAVING INSTRUCTION WITH SELECTIVE USE OF SPECIAL REGISTER AS A SOURCE OPERAND ACCORDING TO INSTRUCTION BITS

An apparatus for fan out of a result of a first instruction can include first through fourth sets of memory cells and circuitry. The first set can be configured to store the result of the first instruction. The second set can be configured to store an operation code of a second instruction. The third set can be configured to store information of the second instruction. The fourth set can be configured to store an operand for the second instruction. The circuitry can be configured to connect the fourth set to an execution unit and to cause, in response to a presence of the information in the third set, the execution unit to be configured to receive a content of the first set as the operand for the second instruction. A format of the second instruction can include a sets of bits designated for the operation code and for the information.