RUN-TIME CODE PARALLELIZATION WITH MONITORING OF REPETITIVE INSTRUCTION SEQUENCES

RUN-TIME CODE PARALLELIZATION WITH MONITORING OF REPETITIVE INSTRUCTION SEQUENCES

A processor includes an execution pipeline and monitoring circuity. The execution pipeline is configured to execute instructions of program code. The monitoring circuity is configured to monitor the instructions in a segment of a repetitive sequence of the instructions so as to construct a specifica...

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser: FRIEDMANN, Jonathan, MANDLER, Alberto, MIZRAHI, Noam, KOREN, Shay
Format: Patent
Sprache:eng ; fre ; ger
Schlagworte:
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Beschreibung
Zusammenfassung:A processor includes an execution pipeline and monitoring circuity. The execution pipeline is configured to execute instructions of program code. The monitoring circuity is configured to monitor the instructions in a segment of a repetitive sequence of the instructions so as to construct a specification of register access by the monitored instructions, to parallelize execution of the repetitive sequence based on the corrected specification, and to terminate monitoring of the instructions and discard the specification in response to detecting a branch mis-prediction in the monitored instructions.