POWERMAP OPTIMIZED THERMALLY AWARE 3D CHIP PACKAGE

POWERMAP OPTIMIZED THERMALLY AWARE 3D CHIP PACKAGE

A semiconductor package (100) includes a substrate (110), an integrated circuit (120), a memory support (140), stacked memory (130), and a lid (150). The integrated circuit has a low power region (124) and a high power region (122). The memory support is disposed on the low power region of the integ...

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Bibliographische Detailangaben
Hauptverfasser: JOUPPI, Norman Paul, KANG, Teck-Gyu, IYENGAR, Madhu Krishnan, MALONE, Christopher Gregory
Format: Patent
Sprache:eng ; fre ; ger
Schlagworte:
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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Beschreibung
Zusammenfassung:A semiconductor package (100) includes a substrate (110), an integrated circuit (120), a memory support (140), stacked memory (130), and a lid (150). The integrated circuit has a low power region (124) and a high power region (122). The memory support is disposed on the low power region of the integrated circuit and is configured to allow a flow of fluid (250) therethrough to conduct heat away from the low power region of the integrated circuit. The lid defines a first port (152, 152a), a second port (152, 152b), and a lid volume fluidly connecting the first port and the second port. The lid volume (160) is configured to house the integrated circuit, the memory support, and the stacked memory, while directing the flow of fluid to flow over the integrated circuit, the memory support, and the stacked memory.