TERMINATION TOPOLOGY OF MEMORY SYSTEM AND ASSOCIATED MEMORY MODULE AND CONTROL METHOD

A memory system (100) includes a memory controller (110) and a memory module (120). The memory controller (110) is arranged for selectively generating at least a clock signal and an inverted clock signal. The memory module (120) includes a first termination resistor (ODT1), a second termination resi...

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Bibliographische Detailangaben
Hauptverfasser:	CHEN, Shang-Pin, HSIEH, Bo-Wei
Format:	Patent
Sprache:	eng ; fre ; ger
Schlagworte:	BASIC ELECTRONIC CIRCUITRY CALCULATING COMPUTING COUNTING ELECTRIC COMMUNICATION TECHNIQUE ELECTRIC DIGITAL DATA PROCESSING ELECTRICITY INFORMATION STORAGE PHYSICS PULSE TECHNIQUE STATIC STORES TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION
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Beschreibung
Zusammenfassung:	A memory system (100) includes a memory controller (110) and a memory module (120). The memory controller (110) is arranged for selectively generating at least a clock signal and an inverted clock signal. The memory module (120) includes a first termination resistor (ODT1), a second termination resistor (ODT2) and a switch module (222), where a first node of the first termination resistor (ODT1) is to receive the clock signal, a first node of the second termination resistor (ODT2) is to receive the inverted clock signal, and the switch module (222) is arranged for selectively connecting or disconnecting a second node of the second termination resistor (ODT2) to a second node of the first termination resistor (ODT1).