CLOCK DATA RECOVERY APPARATUS AND METHOD CAPABLE OF REDUCING MORE NOISE AS WELL AS TRACKING LARGER FREQUENCY OFFSETS

A clock data recovery apparatus (100, 200) includes an oscillator (105), a sampler circuit (110), and a frequency control circuit (115, 215). The oscillator generates a clock signal (SCLK) according to a bias voltage (VB). The sampler circuit (110) samples an input data signal (Sin) to generate a sa...

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Bibliographische Detailangaben
Hauptverfasser:	CHO, Yi-Hsien, YEH, Tse-Hsien
Format:	Patent
Sprache:	eng ; fre ; ger
Schlagworte:	AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATIONOF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES BASIC ELECTRONIC CIRCUITRY ELECTRIC COMMUNICATION TECHNIQUE ELECTRICITY TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION
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Beschreibung
Zusammenfassung:	A clock data recovery apparatus (100, 200) includes an oscillator (105), a sampler circuit (110), and a frequency control circuit (115, 215). The oscillator generates a clock signal (SCLK) according to a bias voltage (VB). The sampler circuit (110) samples an input data signal (Sin) to generate a sampling signal (Ssample) according to the clock signal (SCLK). The frequency control circuit (115, 215) generates the bias voltage (VB) by performing integration calculation, digital-to-analog conversion, and low-pass filtering for the sampling signal (Ssample).