ULTRA WIDEBAND TRUE TIME DELAY LINES
A time delay circuit comprising: a first substrate (92) including a top planar surface and a bottom surface; a delay line (98) formed on the top planar surface of the first substrate (92) and including a first end and a second end; a metal layer (100) formed on the bottom surface of the first substr...
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| creator | Lan, Xing Kintis, Mark Hansen, Chad |
| description | A time delay circuit comprising:
a first substrate (92) including a top planar surface and a bottom surface;
a delay line (98) formed on the top planar surface of the first substrate (92) and including a first end and a second end;
a metal layer (100) formed on the bottom surface of the first substrate (92);
a plurality of first vias (102) extending through the first substrate (92) and being electrically coupled to the delay line (98);
a second substrate (94) including a top planar surface and a bottom surface, said second substrate (94) being spaced apart from the first substrate (92) and defining an air gap therebetween;
a multi-bit switched circuit (114) formed on the top planar surface of the second substrate (94);
and a plurality of inter-cavity interconnections (104) electrically coupled to the multi-bit circuit (114) and the metal layer (100) on the bottom surface of the first substrate (92) and extending through the air gap. |
| format | Patent |
| fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_EP3168926B1</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>EP3168926B1</sourcerecordid><originalsourceid>FETCH-epo_espacenet_EP3168926B13</originalsourceid><addsrcrecordid>eNrjZFAJ9QkJclQI93RxdXL0c1EICQp1VQjx9HVVcHH1cYxU8PH0cw3mYWBNS8wpTuWF0twMCm6uIc4euqkF-fGpxQWJyal5qSXxrgHGhmYWlkZmTobGRCgBAClWIno</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>ULTRA WIDEBAND TRUE TIME DELAY LINES</title><source>esp@cenet</source><creator>Lan, Xing ; Kintis, Mark ; Hansen, Chad</creator><creatorcontrib>Lan, Xing ; Kintis, Mark ; Hansen, Chad</creatorcontrib><description>A time delay circuit comprising:
a first substrate (92) including a top planar surface and a bottom surface;
a delay line (98) formed on the top planar surface of the first substrate (92) and including a first end and a second end;
a metal layer (100) formed on the bottom surface of the first substrate (92);
a plurality of first vias (102) extending through the first substrate (92) and being electrically coupled to the delay line (98);
a second substrate (94) including a top planar surface and a bottom surface, said second substrate (94) being spaced apart from the first substrate (92) and defining an air gap therebetween;
a multi-bit switched circuit (114) formed on the top planar surface of the second substrate (94);
and a plurality of inter-cavity interconnections (104) electrically coupled to the multi-bit circuit (114) and the metal layer (100) on the bottom surface of the first substrate (92) and extending through the air gap.</description><language>eng ; fre ; ger</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRICITY ; RESONATORS, LINES, OR OTHER DEVICES OF THE WAVEGUIDE TYPE ; WAVEGUIDES</subject><creationdate>2018</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20180801&DB=EPODOC&CC=EP&NR=3168926B1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20180801&DB=EPODOC&CC=EP&NR=3168926B1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Lan, Xing</creatorcontrib><creatorcontrib>Kintis, Mark</creatorcontrib><creatorcontrib>Hansen, Chad</creatorcontrib><title>ULTRA WIDEBAND TRUE TIME DELAY LINES</title><description>A time delay circuit comprising:
a first substrate (92) including a top planar surface and a bottom surface;
a delay line (98) formed on the top planar surface of the first substrate (92) and including a first end and a second end;
a metal layer (100) formed on the bottom surface of the first substrate (92);
a plurality of first vias (102) extending through the first substrate (92) and being electrically coupled to the delay line (98);
a second substrate (94) including a top planar surface and a bottom surface, said second substrate (94) being spaced apart from the first substrate (92) and defining an air gap therebetween;
a multi-bit switched circuit (114) formed on the top planar surface of the second substrate (94);
and a plurality of inter-cavity interconnections (104) electrically coupled to the multi-bit circuit (114) and the metal layer (100) on the bottom surface of the first substrate (92) and extending through the air gap.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRICITY</subject><subject>RESONATORS, LINES, OR OTHER DEVICES OF THE WAVEGUIDE TYPE</subject><subject>WAVEGUIDES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2018</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZFAJ9QkJclQI93RxdXL0c1EICQp1VQjx9HVVcHH1cYxU8PH0cw3mYWBNS8wpTuWF0twMCm6uIc4euqkF-fGpxQWJyal5qSXxrgHGhmYWlkZmTobGRCgBAClWIno</recordid><startdate>20180801</startdate><enddate>20180801</enddate><creator>Lan, Xing</creator><creator>Kintis, Mark</creator><creator>Hansen, Chad</creator><scope>EVB</scope></search><sort><creationdate>20180801</creationdate><title>ULTRA WIDEBAND TRUE TIME DELAY LINES</title><author>Lan, Xing ; Kintis, Mark ; Hansen, Chad</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_EP3168926B13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng ; fre ; ger</language><creationdate>2018</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRICITY</topic><topic>RESONATORS, LINES, OR OTHER DEVICES OF THE WAVEGUIDE TYPE</topic><topic>WAVEGUIDES</topic><toplevel>online_resources</toplevel><creatorcontrib>Lan, Xing</creatorcontrib><creatorcontrib>Kintis, Mark</creatorcontrib><creatorcontrib>Hansen, Chad</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Lan, Xing</au><au>Kintis, Mark</au><au>Hansen, Chad</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>ULTRA WIDEBAND TRUE TIME DELAY LINES</title><date>2018-08-01</date><risdate>2018</risdate><abstract>A time delay circuit comprising:
a first substrate (92) including a top planar surface and a bottom surface;
a delay line (98) formed on the top planar surface of the first substrate (92) and including a first end and a second end;
a metal layer (100) formed on the bottom surface of the first substrate (92);
a plurality of first vias (102) extending through the first substrate (92) and being electrically coupled to the delay line (98);
a second substrate (94) including a top planar surface and a bottom surface, said second substrate (94) being spaced apart from the first substrate (92) and defining an air gap therebetween;
a multi-bit switched circuit (114) formed on the top planar surface of the second substrate (94);
and a plurality of inter-cavity interconnections (104) electrically coupled to the multi-bit circuit (114) and the metal layer (100) on the bottom surface of the first substrate (92) and extending through the air gap.</abstract><oa>free_for_read</oa></addata></record> |
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| subjects | BASIC ELECTRIC ELEMENTS ELECTRICITY RESONATORS, LINES, OR OTHER DEVICES OF THE WAVEGUIDE TYPE WAVEGUIDES |
| title | ULTRA WIDEBAND TRUE TIME DELAY LINES |
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