ULTRA WIDEBAND TRUE TIME DELAY LINES
A time delay circuit comprising: a first substrate (92) including a top planar surface and a bottom surface; a delay line (98) formed on the top planar surface of the first substrate (92) and including a first end and a second end; a metal layer (100) formed on the bottom surface of the first substr...
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| Hauptverfasser: | , , |
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| Format: | Patent |
| Sprache: | eng ; fre ; ger |
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| Zusammenfassung: | A time delay circuit comprising:
a first substrate (92) including a top planar surface and a bottom surface;
a delay line (98) formed on the top planar surface of the first substrate (92) and including a first end and a second end;
a metal layer (100) formed on the bottom surface of the first substrate (92);
a plurality of first vias (102) extending through the first substrate (92) and being electrically coupled to the delay line (98);
a second substrate (94) including a top planar surface and a bottom surface, said second substrate (94) being spaced apart from the first substrate (92) and defining an air gap therebetween;
a multi-bit switched circuit (114) formed on the top planar surface of the second substrate (94);
and a plurality of inter-cavity interconnections (104) electrically coupled to the multi-bit circuit (114) and the metal layer (100) on the bottom surface of the first substrate (92) and extending through the air gap. |
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