STRUCTURE AND METHOD OF BATCH-PACKAGING LOW PIN COUNT EMBEDDED SEMICONDUCTOR CHIPS

A method for fabricating packaged semiconductor devices in panel format. A flat panel sheet dimensioned for a set of contiguous chips includes a stiff substrate of an insulating plate, and a tape having a surface layer of a first adhesive releasable at elevated temperatures, a core base film, and a bottom layer with a second adhesive attached to the substrate. Attaching a set onto the first adhesive layer, the chip terminals having terminals with metal bumps facing away from the first adhesive layer. Laminating low CTE insulating material to fill gaps between the bumps and to form an insulating frame surrounding the set. Grinding lamination material to expose the bumps. Plasma-cleaning assembly, sputtering uniform metal layer across assembly, optionally plating metal layer, and patterning metal layer to form rerouting traces and extended contact pads.