COMPUTATION CIRCUIT, ENCODING CIRCUIT, AND DECODING CIRCUIT
In order to speed up computation processing, memories (M0 to M15) retain data blocks on which exclusive logical OR computation is performed, and selection circuits (2a to 2p) receive a selection signal and select two or more data blocks for use in exclusive logical OR computation from among a plural...
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| Format: | Patent |
| Sprache: | eng ; fre ; ger |
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| Zusammenfassung: | In order to speed up computation processing, memories (M0 to M15) retain data blocks on which exclusive logical OR computation is performed, and selection circuits (2a to 2p) receive a selection signal and select two or more data blocks for use in exclusive logical OR computation from among a plurality of data blocks read from the memories (M0 to M15) on the basis of the selection signal, and XOR circuits (3a to 3o) (exclusive logical OR computation circuits) perform exclusive logical OR computation based on the two or more data blocks selected by the selection circuits (2a to 2p). |
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