METHODS OF TUNNEL OXIDE LAYER FORMATION IN 3D NAND MEMORY STRUCTURES AND ASSOCIATED DEVICES

METHODS OF TUNNEL OXIDE LAYER FORMATION IN 3D NAND MEMORY STRUCTURES AND ASSOCIATED DEVICES

3D NAND memory structures and related method are provided. In some embodiments such structures can include a control gate material and a floating gate material disposed between a first insulating layer and a second insulating layer, an interpoly dielectric (IPD) layer disposed between the floating g...

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Bibliographische Detailangaben
Hauptverfasser: HOPKINS, John, FAN, Darwin, KHANDEKAR, Anish, SURTHI, Shyam, HALLER, Gordon, KOKA, Sateesh
Format: Patent
Sprache:eng ; fre ; ger
Schlagworte:
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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Zusammenfassung:3D NAND memory structures and related method are provided. In some embodiments such structures can include a control gate material and a floating gate material disposed between a first insulating layer and a second insulating layer, an interpoly dielectric (IPD) layer disposed between the floating gate material and control gate material such that the IPD layer electrically isolates the control gate material from the floating gate material, and a tunnel dielectric material deposited on the floating gate material opposite the control gate material.