PROCESSOR LOGIC AND METHOD FOR DISPATCHING INSTRUCTIONS FROM MULTIPLE STRANDS

PROCESSOR LOGIC AND METHOD FOR DISPATCHING INSTRUCTIONS FROM MULTIPLE STRANDS

A processor includes logic to fetch an instruction stream divided into a plurality of strands for loading on one or more execution ports, identify a plurality of pending instructions, determine which of the strands are active, determine a program order of each of the pending instructions, and match...

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser: SIVTSOV, Alexey, BABAYAN, Boris A, KOSAREV, Nikolay, SHISHLOV, Sergey Y, BUTUZOV, Alexander V, IYER, Jayesh
Format: Patent
Sprache:eng ; fre ; ger
Schlagworte:
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Beschreibung
Zusammenfassung:A processor includes logic to fetch an instruction stream divided into a plurality of strands for loading on one or more execution ports, identify a plurality of pending instructions, determine which of the strands are active, determine a program order of each of the pending instructions, and match the pending instructions to the execution ports based upon the program order of each pending instruction and whether each strand is active. Each pending instruction is at a respective head of one of the strands.