STATIC DATA BUS ADDRESS ALLOCATION

The present invention relates to a data bus node integrated circuit (1) comprising at least one static address selection terminal (3) and a detecting circuit (4) for detecting a state of the address selection terminal (3). The IC also comprises a communication circuit (5) for data communication over a data bus (9). This circuit (5) is adapted for determining a node address identifier taking the detected state of the at least one static address selection terminal (3) into account. The detecting circuit (4) is adapted for detecting the state of the address selection terminal by determining whether the address selection terminal (3) is in a floating state, a power supply voltage state or a ground voltage state.