A METHOD, APPARATUS AND SYSTEM FOR DYNAMICALLY CONTROLLING AN ADDRESSING MODE FOR A CACHE MEMORY

A METHOD, APPARATUS AND SYSTEM FOR DYNAMICALLY CONTROLLING AN ADDRESSING MODE FOR A CACHE MEMORY

In an embodiment, a first portion of a cache memory is associated with a first core. This first cache memory portion is of a distributed cache memory, and may be dynamically controlled to be one of a private cache memory for the first core and a shared cache memory shared by a plurality of cores (in...

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser: BIAN, Zhaojuan, ZHOU, Wei, WANG, Kebing, WANG, Zhihong
Format: Patent
Sprache:eng ; fre ; ger
Schlagworte:
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Beschreibung
Zusammenfassung:In an embodiment, a first portion of a cache memory is associated with a first core. This first cache memory portion is of a distributed cache memory, and may be dynamically controlled to be one of a private cache memory for the first core and a shared cache memory shared by a plurality of cores (including the first core) according to an addressing mode, which itself is dynamically controllable. Other embodiments are described and claimed.