LATENCY SENSITIVE SOFTWARE INTERRUPT AND THREAD SCHEDULING

Various embodiments provide an ability to schedule latency-sensitive tasks based, at least in part, upon one or more processor cores usage metrics. Some embodiments gather information associated with whether one or more processor cores are in a heavily loaded state. Alternately or additionally, some...

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Bibliographische Detailangaben
Hauptverfasser: ZHU, Danyu, WATERS, Bradley M
Format: Patent
Sprache:eng ; fre ; ger
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Zusammenfassung:Various embodiments provide an ability to schedule latency-sensitive tasks based, at least in part, upon one or more processor cores usage metrics. Some embodiments gather information associated with whether one or more processor cores are in a heavily loaded state. Alternately or additionally, some embodiments gather information identifying latency-sensitive tasks. Task(s) can be (re)assigned to different processor core(s) for execution when it has been determined that an originally assigned processor core has exceeded a usage threshold.