Method and arrangement for reducing current stress in intermediate circuit of three-level inverter

Method and arrangement for reducing current stress in intermediate circuit of three-level inverter

A method and arrangement for reducing current stress in an intermediate circuit of a three-level inverter comprising a first capacitance and a second capacitance, the arrangement comprising means (10) for modifying a voltage reference U 1 of the inverter by adding a third harmonic U 3 to the voltage...

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser: HAKKARAINEN, ANNA, VIITANEN, TERO, ALAHUHTALA, JARNO, HEIKKILÄ, SAMULI
Format: Patent
Sprache:eng ; fre ; ger
Schlagworte:
APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC,OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWERSUPPLY SYSTEMS
CONTROL OR REGULATION THEREOF
CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUTPOWER
CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
ELECTRICITY
GENERATION
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Beschreibung
Zusammenfassung:A method and arrangement for reducing current stress in an intermediate circuit of a three-level inverter comprising a first capacitance and a second capacitance, the arrangement comprising means (10) for modifying a voltage reference U 1 of the inverter by adding a third harmonic U 3 to the voltage reference, means (20) for pulse width modulation controlling the inverter according to the modified voltage reference, and means (30) for adjusting the amplitude and/or the phase difference of the third harmonic added to the voltage reference of the inverter such that a quantity indicating a magnitude of a current stress on the first capacitance and the second capacitance at a frequency of the third harmonic is reduced substantially to a minimum or below a predetermined level.