Semiconductor device with a chip bonded to a lead frame with a sintered Ag layer, wherein a resin fillet covers the sintered Ag layer and a part of a side surface of the chip and wherein chip electrodes are bonded to leads, as well as method of manufacturing the same
A semiconductor device (20, 24, 29, 32, 35, 38) includes a die pad (6), a wide gap semiconductor chip (SiC or GaN) (1) mounted on the die pad (6), a porous first sintered Ag layer (16) bonding the die pad (6) and the chip (1), and a reinforcing resin portion (17) covering a surface of the first sint...
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Format: | Patent |
Sprache: | eng ; fre ; ger |
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Zusammenfassung: | A semiconductor device (20, 24, 29, 32, 35, 38) includes a die pad (6), a wide gap semiconductor chip (SiC or GaN) (1) mounted on the die pad (6), a porous first sintered Ag layer (16) bonding the die pad (6) and the chip (1), and a reinforcing resin portion (17) covering a surface of the first sintered Ag layer (16) and a part of a side surface of the chip (1) and formed in a fillet shape. The semiconductor device (20, 24, 29, 32, 35, 38) further includes electrodes (1g, 1h, 2, 3, 4) on its main (1a) and back (1b) surfaces, the electrodes (1g, 1h, 2, 3, 4) being electrically connected to leads (7, 9, 11, 39), wherein the electrical connection at the front side is a wire (18, 19, 25, 26) connection and the electrical connection at the back side is the first sintered Ag layer (16). A porous second sintered Ag layer (36) or a second resin portion (30) reinforces the wire bonding portion on the electrode (1g, 2, 3). The semiconductor device (20, 24, 29, 32, 35, 38) further includes a sealing body (third resin) (14) which covers the chip (1), the first sintered Ag layer (16), and a part of the die pad (6). |
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