SYSTEMS AND METHODS FOR VOID REDUCTION IN A SOLDER JOINT

In accordance with one or more aspects, a method of reducing void formation in a solder joint may comprise applying a solder paste deposit to a substrate, placing a solder preform in the solder paste deposit, disposing a device on the solder preform and the solder paste deposit, and processing the s...

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Bibliographische Detailangaben
Hauptverfasser:	TORMEY, ELLEN, S, DE MONCHY, MICHIEL A, KOEP, PAUL, J
Format:	Patent
Sprache:	eng ; fre ; ger
Schlagworte:	CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR ELECTRICITY MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS PRINTED CIRCUITS
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Beschreibung
Zusammenfassung:	In accordance with one or more aspects, a method of reducing void formation in a solder joint may comprise applying a solder paste deposit to a substrate, placing a solder preform in the solder paste deposit, disposing a device on the solder preform and the solder paste deposit, and processing the solder paste deposit and the solder preform to form the solder joint between the device and the substrate. In some aspects, the substrate is a printed circuit board and the device is an integrated circuit package.