INTEGRATING INTELLECTUAL PROPERTY (IP) BLOCKS INTO A PROCESSOR

In one embodiment, the present invention includes apparatus that is formed on a single semiconductor die having one or more cores, a memory controller, and a hub coupled to the memory controller. The hub includes multiple fabrics each to communicate with a peripheral controller via a target interfac...

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Bibliographische Detailangaben
Hauptverfasser: TRAN, JEFF, V, NIMMALA, PRASHANTH, GREINER, ROBERT, J, VAKHARWALA, RUPIN, H, WOOD, AIMEE, D, LOOI, LILY, P, SONG, MARCUS, W, BEAVENS, JAMES, A
Format: Patent
Sprache:eng ; fre ; ger
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Beschreibung
Zusammenfassung:In one embodiment, the present invention includes apparatus that is formed on a single semiconductor die having one or more cores, a memory controller, and a hub coupled to the memory controller. The hub includes multiple fabrics each to communicate with a peripheral controller via a target interface and a master interface according to a first protocol, and where the fabrics are serially coupled via a first plurality of target interfaces in an upstream direction and a second plurality of target interfaces in a downstream direction. Other embodiments are described and claimed.